The present invention relates to an electronic package, also known as "module".
In such a package or module, e.g., such as described in IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. CHMT-7, No. 2, p. 193 ff, June 1984, a silicon substrate equipped with a plurality of chips comprising integrated circuits is placed roughly centrally on a bigger ceramic plate. This ceramic plate contains in its border section the connector pins connected via conductive lines on the ceramic plate to the chip contact points on the silicon substrate.
The manufacture of such a module is relatively complex, as it consists of a plurality of parts which originally are separate units and have subsequently to be interconnected, not only because the substrate carrying the chips and the plate with the connector pins have to be made separately in individual product lines, but also because it is a relatively complex process to insert the connector pins in the ceramic plate and/or to bring the conductive lines through the ceramic plate to the connector pins. Another disadvantage of such a package structure is that, owing to the arrangement and the necessary spacing of the connector pins relative to each other, the module base surface is much larger than required for the necessary base surface of the chips that occupy the substrate. Thus, the packing density of the chips that are to be provided on a plug-in card is not determined by their base surface but by the packing density of the connector pins which is roughly ten times higher. Furthermore, due to the above mentioned difficulty of placing the conductive lines on the chip-covered substrate surface the connector pins cannot be provided directly beneath the chips.
A package or module, respectively, of the above specified type is also known from IBM Technical Disclosure Bulletin Vol. 24, No. 12, page 6388 ff., May 1982. With this module, the chips are provided on a silicon substrate placed on a mechanically fixed interposer having on its lower side the pin carrier plate. For electrically connecting the chips to the connector pins, a multi-strand cable is provided which extends from parallel conductors arranged in the edge section of the silicon substrate round the lateral edge of the interposer and between the lower side of the interposer and the opposite surface of the pin carrier plate to the individual back ends of the connector pins protruding through the pin carrier plate.
Although with such an arrangement of the conductors between the chips and the connector pins the conductors no longer have to be arranged in a complex design through a carrier plate or similar element, with the lower chip surfaces being equally designed for holding connector pins, there still is a discrepancy between the base surface required for the chips and the module base surface required for the connector pins. Furthermore, the individual components have also to be made and subsequently assembled in separate production lines.
Another disadvantage of the two above specified known packages is that these can only be tested after the assembly of the individual components, which means that for the elimination of potential minor defects, these cannot be disassembled without being demolished. The same applies to future module defects during operation.
It is therefore an object of the present invention to provide an electronic package or module of the above specified type which is less complex in manufacture and which, with the same or comparable performance, requires a much reduced surface area.